1. Field of the Invention
The present invention relates to electronic components, and more particularly to integrated capacitors.
2. Description of Related Art
Integrated capacitors refer to capacitors built on integrated circuits. Integrated capacitors are used for several reasons. One reason is to provide compensation capacitance for an operational amplifier in order to roll off high frequency response for stability purposes. A second reason is to provide a large amount of capacitance between signals. A third reason is to provide a large amount of capacitance between a signal and a power supply or ground. A fourth reason is to provide a large amount of capacitance between power supplies or between a power supply and ground. These types of capacitors are known as decoupling capacitors.
Integrated capacitors are often implemented as parallel-plate capacitors using vertically displaced conducting layers such as metal-1 and metal-2, metal-1 and polysilicon used for the gate material in a CMOS process, or conducting layers in a bipolar process. Integrated capacitors are also implemented as junction capacitors using reverse-biased PN junctions. Furthermore, integrated capacitors are implemented as MOS transistor capacitors, with the gate providing one plate and an inversion layer in the channel providing the other. These techniques are further described below.
FIG. 1 shows a cross-sectional view of conventional parallel-plate capacitor 10 which includes conductive layer 12, conductive layer 14, and dielectric layer 16 therebetween. Conductive layers 12 and 14 provide the capacitive plates, and dielectric layer 16 provides the dielectric therebetween. Capacitor 10 is disposed over semiconductor substrate 18. Terminals 20 and 22 are depicted schematically and coupled to conductive layers 12 and 14, respectively. Conductive layers 12 and 14 and dielectric layer 16 can be a wide variety of materials. For instance, conductive layers 12 and 14 can be metal, in which case capacitor 10 forms a metal-metal capacitor. Conductive layer 12 can be metal and conductive layer 14 can be polysilicon, in which case capacitor 10 forms a metal-polysilicon capacitor. In addition, conductive layers 12 and 14 can be polysilicon, in which case capacitor 10 forms a polysilicon-polysilicon capacitor. The dielectric is typically silicon dioxide. For instance, a thin oxide layer can be deposited or thermally grown between polysilicon layers. Metal-metal and metal-polysilicon capacitors provide good frequency response because the capacitive plates are relatively highly conductive and therefore provide a low RC product for low impedance at high frequency. However, metal-metal and metal-polysilicon capacitors require a large amount of chip area for a relatively small amount of capacitance due to the thick dielectric layer between the conductive layers. Polysilicon-polysilicon capacitors provide moderately high capacitance per unit area, and in addition, the polysilicon layers can be heavily doped to provide moderately good conductivity in the capacitive plates for a medium level of frequency response. However, it is difficult to form a thin oxide of high quality between the polysilicon layers due to surface roughness of the polysilicon.
FIG. 2 shows a cross-sectional view of conventional junction capacitor 30 that includes N+ heavily doped region 32 in P- device region 34, such as a P-well in a semiconductor substrate. Capacitor 30 also includes positive terminal 36 depicted schematically and coupled to heavily doped region 32, and negative terminal 38 depicted schematically and coupled to device region 34. A drawback to capacitor 30, however, is that the depletion layer separating heavily doped region 32 and device region 34 might not be thin enough to provide the desired capacitance. Although providing heavily doped region 32 with extremely high doping leads to a thinner depletion region, it also decreases the breakdown voltage, increases voltage dependence, and results in relatively resistive capacitive plates with poor frequency response.
FIGS. 3, 4 and 5 show a schematic diagram, a cross-sectional view, and a top plan view, respectively, of conventional N-channel MOS transistor capacitor 40. As is seen, capacitor 40 includes P- device region 42, such as a P-well in a P- semiconductor substrate. Capacitor 40 also includes oxide layer 44 on a central portion of device region 42, N+ polysilicon gate 46 on oxide layer 44, N- lightly doped source/drain region 48 in device region 42 and outside and aligned with the sidewalls of polysilicon gate 46, oxide spacer 50 over lightly doped source/drain region 48 and adjacent to the sidewalls of polysilicon gate 46, and N+ heavily doped source/drain region 52 in device region 42 and outside and aligned with the outer edges of oxide spacer 50. Capacitor 40 also includes positive terminal 54 depicted schematically and coupled to polysilicon gate 46, and negative terminal 56 depicted schematically and coupled to heavily doped source/drain region 52 and to P+ well tap 58 in device region 42. Terminals 54 and 56 are coupled to polysilicon gate 46, heavily doped source/drain region 52 and well tap 58 through conductive vias 60, 62 and 64, respectively, in contact holes of a dielectric layer (not shown). For convenience of illustration, other conductive vias and dielectric isolation between adjacent device regions are not shown.
FIGS. 6, 7 and 8 show a schematic diagram, a cross-sectional view, and a top plan view, respectively, of conventional P-channel MOS transistor capacitor 70. As is seen, capacitor 70 includes N- device region 72, such as an N-well in a P- semiconductor substrate. Capacitor 70 also includes oxide layer 74 on central portion of device region 72, P+ polysilicon gate 76 on oxide layer 74, P- lightly doped source/drain region 78 in device region 72 and outside and aligned with the sidewalls of polysilicon gate 76, oxide spacer 80 over lightly doped source/drain region 78 and adjacent to the sidewalls of polysilicon gate 76, and P+ heavily doped source/drain region 82 in device region 72 and outside and aligned with the outer edges of oxide spacer 80. Capacitor 70 also includes positive terminal 84 depicted schematically and coupled to heavily doped source/drain region 82 and to P+ well tap 88 in device region 72, and negative terminal 86 depicted schematically and coupled to polysilicon gate 76. Terminals 84 and 86 are coupled to polysilicon gate 76, heavily doped source/drain region 82 and well tap 88 through conductive vias 90, 92 and 94, respectively, in contact holes of a dielectric layer (not shown). For convenience of illustration, other conductive vias and dielectric isolation between adjacent device regions are not shown.
During the operation of transistor capacitors 40 and 70, the voltage applied to the positive terminal is greater than the voltage applied to the negative terminal, and the voltage drop between the positive and negative terminals modulates the net carrier concentration in the channel to create an inversion layer in the channel (the classical enhancement-mode field effect). This biases the transistor in the triode region, with the gate providing one plate and the inversion layer providing the other.
A problem which arises in N-channel transistor capacitor 40 is that the voltage across the gate oxide is relatively high due to the Fermi level difference between the gate and the substrate. Although P-channel transistor capacitor 70 has the same Fermi potential problem, a further problem is that the gate is biased negatively with respect to the substrate in order to cause inversion, and since the bottom of a polysilicon gate tends to be rough relative to the smooth surface of the single-crystal silicon substrate, electrons are more easily emitted from the points of the roughness due to the field enhancement at the tips. This significantly degrades the voltage-bearing capacity of the gate oxide, requiring a thicker gate oxide with consequently lower capacitance.
Moreover, both capacitor 40 and capacitor 70 have relatively high resistance in the inversion layer, which limits frequency response. In addition, these capacitors have a limited breakdown voltage, or alternatively, the lifetime of the gate oxide with reference to Time-Dependent Dielectric Breakdown (TDDB) is low.
Accordingly, a need exists for an improved integrated capacitor.